Project Experience

 

The designs listed below represent a sampling of the projects undertaken over the last 14 years.  They illustrate the wide range of applications and technologies we have been involved in.

ASIC/FPGA and Hardware Designs

Firmware and Software Designs

 

  ASIC/FPGA and Hardware Designs

Electronic Speed Control-1 

Designed for radio controlled aircraft, the 3-speed digital motor controller was very compact and lightweight, yet could handle high motor currents.  The design featured digital pulse-width modulation (PWM), low-resistance power MOSFETs, opto-isolation between the RF receiver and motor circuits, and high-temperature silicone wiring.

Electronic Speed Control-2    

Designed for an electric bicycle, the fully proportional digital motor controller was compact and high-performance.  The intelligent controller featured an 8-bit RISC microcontroller, digital pulse-width modulation (PWM), remote thermal sensor interface, low-resistance power MOSFETs, and thermal-shutdown protection.

SCSI Controller Chipset          

Designed the data path and interface logic for a caching, EISA-bus SCSI controller.  The FPGA-based chip set featured multiple data FIFOs, a multi-port data bus switch, a DRAM controller state machine, a SCSI controller interface state machine, and local processor interface logic.  The design was implemented in Actel FPGAs.

CDMA System Controller Chip        

Designed the system controller ASIC used in the handset and base station of a 24-user CDMA wireless phone system.  The design featured a digital feedback control loop, with an NCO and programmable gain coefficients, to acquire and track the CDMA signal, a complete digital communications modem with 3-bit Golay Code error detection and correction, 12-bit DSP input and output filtering, BPSK signal modulation and demodulation, Costas error tracking, and a digital Alarm Clock for power savings in sleep mode.  The ASIC was successfully fabricated and tested with dual foundries:  KLSI and Samsung, in their 0.5m ASIC processes.

PC104 Control and Data Acquisition Chips        

Designed over a dozen system controller FPGAs for PC104 CPU and data acquisition systems.  The designs featured PC104 bus controllers, DMA engines, support for several types of DAC and ADC devices, logic for supporting internal and external FIFOs, I2C controllers, and PWM generators.  The designs were implemented in Actel and Xilinx FPGAs.

High-Performance Motion Controller Chips        

Designed four high-speed digital ASICs used in DSP-based motion control.  The designs featured on-chip 120 MHz phase-locked loops, high-resolution PWM and PFM motor control logic, high-resolution position and velocity feedback interfaces, and control logic for an industry standard high-speed optical ring network.  The designs were successfully fabricated in LSI Logic's 0.6m ASIC process.

High-Performance RAID Memory Controller        

Designed a high-performance SDRAM memory cache controller ASIC used in a RAID controller system.  The design featured dual system bus interfaces, a Failover bus controller, a SDRAM controller, and an internal data cache system for optimizing the memory access bandwidth.  The design was successfully fabricated in KLSI's 0.35m ASIC process.

High-Performance 8051 Processor Core        

Designed an optimized 8051 microcontroller core for high-performance embedded applications.  The design featured fully instruction set compatibility with the industry standard microcontroller, optimized logic for low power and low gate-count, and an optimized architecture with most instructions executed in two clock cycles versus 12 to 24 in the original design.

High-Performance Bluetooth® Baseband Controller        

Designed a complete Bluetooth® baseband controller optimized for low power and low gate-count.  The design featured our optimized 8051 microcontroller with 36K of ROM and 4K of RAM, a 128-bit encryption engine, a SCO audio channel with 16-bit DSP filtering for optimizing audio quality, support for a full eight-device piconet, all three low-power modes, and full authentication and encryption functions.  The design was successfully prototyped in a single Xilinx FPGA and verified for interoperability with industry Bluetooth® devices.

Bluetooth® Baseband Development Board  

Designed a development board for the system-level validation of the hardware and software of the Bluetooth® baseband controller and embedded firmware.  The board featured a configurable interface to several supported Bluetooth® radio chips, an audio CODEC and headset jack, a status display LCD, and a USB interface to the host PC. 

 

  Firmware and Software Designs

Wireless 900 MHz Phone Firmware        

Designed the firmware for a consumer 900 MHz wireless phone.  The program, written in assembly, ran on an 8-bit RISC microcontroller.  The firmware was responsible for channel programming and scanning, keypad scanning, and ringer/audio controls. 

Data Transfer and BER Test Software        

Designed a Windows®-based GUI for controlling a wireless CDMA phone system for test and diagnostic purposes.  The suite of tools, written in C++, permitted internal visibility and diagnostic control for the CDMA system controller ASIC.  The user interface software communicated with the ASIC via the parallel port on the PC.  The tools featured a variety of data transfer tests, BER tests, and real-time visibility of all control and status registers within the ASIC.

Custom ATPG Software        

Designed a customized Automatic Test Pattern Generator software tool.  The program, written in C, featured a Verilog netlist parser, an ATPG algorithm, test pattern compactor, and test pattern output formatter.  The software tool was used successfully to generate ASIC test patterns for several complex logic blocks.

Bluetooth® Baseband Embedded Firmware        

Designed the embedded Host Controller Interface (HCI) and Link Manager (LM) firmware used in the Bluetooth® baseband controller.  The firmware, written in C, implemented all of the supported HCI and LM functions defined in the Bluetooth® specification 1.1.  The partitioning of the firmware and hardware within the baseband controller was designed to maximize performance while minimizing power and code size.  The result was a full-featured design with 36K of program ROM, 4K of program RAM, and firmware that ran efficiently on the embedded 8051 CPU.

Bluetooth® HCI Control Panel Software        

Designed  a Windows®-based GUI for controlling the Bluetooth® baseband development board.  The suite of tools, written in C++, implemented all of the HCI commands, allowing the user to generate any HCI command and data packet to the baseband controller.  HCI status and response packets are also displayed in the console window.  Higher level L2CAP and RFCOMM software tests provided the user with a selection of application and diagnostic functions.  The user interface software communicated with the Bluetooth® baseband development board via the USB port on the PC.

 

 


 

Home Products & Services Intellectual Property Development Kits Technical Documents

 Support Contact

© Copyright 2003. Young Engineering.